Power Electronics

A cybersecure power router will be developed to demonstrate embedded cybersecurity for grid-connected power electronics.  Communication, operation, control, hardware protection, firmware integrity, and other aspects of design and use will be researched within the context of embedded processing and grid-connectivity.

This project involves the design and construction of a SiC-based direct power electronics interface for a battery energy storage system (BESS), which is to be integrated into a 13.8 kV medium-voltage distribution system.  Normally, to interface a BESS to a medium-voltage distribution line, a step-up transformer is required to boost the inverter output voltage.  The use of the transformer provides convenient isolation, however using a transformer to meet medium-voltage inverter insulation requirements leads to substantially higher leakage inductance.
Recent advances in high voltage power semiconductor devices, medium-voltage (>10 kV) SiC power modules present an opportunity to realize a transformerless interface, shown in the Fig.1.  Transformerless topologies, and the use of wide bandgap devices, have the potential for reducing cost and size of passive components for the medium-voltage inverter. To satisfy the medium voltage basic insulation level (BIL) requirements for the power electronics interface, modular multilevel cascade (MMC) inverters provide a better solution. This battery energy storage system interface will also include fault protection circuitry and communication protocols. The performance of the control algorithms for a BESS equipment will be tested through an experimental prototype at the National Center for Reliable Electric Power Transmission (NCREPT) using the 13.8 kV distribution system.

This project addresses the main optimization and design of gate drivers for high-voltage Silicon Carbide power MOSFETs. The main issues associated with these gate drivers are isolation, protection, dv/dt, di/dt and EMI tolerance. The switching performance and ratings of high-voltage SiC MOSFETs are used to determine the gate driver’s needs. Ongoing research and industry needs are considered in the optimization of the gate driver board design. Gate driver circuit designs are simulated and tested in a double-pulse test (DPT) at desired load conditions. The majority of tests are performed at NCREPT (National Center for Reliable Electric Power Transmission) for high-voltage testing. This testbed development will also serve as a standard for future research projects in this area, as high accuracy and minimized parasitics are a concern. In addition to the optimization of the main driver functions, alternate laminate technologies will be considered including the use of LTCC (low-temperature co-fired ceramic) to increase voltage isolation and temperature-handling capability.